Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part I: Theoretical Derivation
نویسندگان
چکیده
An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by dividing into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and highdielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization.
منابع مشابه
Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part II: Quantitative Analysis
Source/drain (S/D) series resistance components and device/process parameters contributing to series resistance are extensively analyzed using advanced model for future CMOS design and technology scaling into the nanometer regime. The total series resistance of a device is found to be very sensitive to the variations of the sidewall thickness, the doping concentration in the deep junction regio...
متن کاملCMOS Scaling into the Nanometer Regime
Starting with a brief review on 0.1m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number f...
متن کاملModeling of High Frequency Noise of Silicon CMOS Transistors for RFIC Design
This work presents high frequency noise measurements and compact modeling for a 90 nm silicon CMOS technology in terms of RF figures of merit (FoMs). Minimum noise figure (NFmin), equivalent noise resistance (Rn), optimum source reflection coefficient (Γopt), thermal noise excess factor as well as a recently introduced FoM for common-source (CS) LNA design are presented from a circuit design pe...
متن کاملDerivation of ionization energy and electron affinity equations using chemical hardness and absolute electronegativity in isoelectronic series
Chemical hardness () and absolute electronegativity () have important applications in chemistry. Inthe conceptual Density Functional theory (DFT), these concepts has been associated with electronicenergy and the relationship with ionization energy (I) and electron affinity (A) of these concepts hasbeen given. In this study, graphical method was used in order to see the relationship with the ato...
متن کاملSuppression of Gate Induced Drain Leakage Current (gidl) by Gate Workfunction Engineering: Analysis and Model
Leakage current reduction is of primary importance as the technology scaling trends continue towards deep sub-micrometer regime. One of the leakage mechanisms which contribute significantly to power dissipation is the Gate Induced Drain Leakage (GIDL). GIDL sets an upper limit on the VLSI MOSFET scaling and may even lead to device breakdown. Thus, in order to improve performance, static power c...
متن کامل